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ALTERA
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| Part No. |
EPC4QC100 EPC16QI100
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| OCR Text |
...d 8) programmable logic device (pld) concurrent configuration mode - Configures multiple plds in parallel - Supports an 8-bit parallel data output on every DCLK cycle Pin-selectable 2-ms or 100-ms power-on reset (POR) time Programmable cloc... |
| Description |
Enhanced Configuration Devices
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| File Size |
257.39K /
36 Page |
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it Online |
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ST Microelectronics
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| Part No. |
PSD4235G2
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| OCR Text |
...includes configurable memories, pld logic and i/o: n dual bank flash memories C 4 mbit of primary flash memory (8 uniform sectors, 32k x 16) C 256 kbit secondary flash memory with 4 sectors C concurrent operation: read from one memory while... |
| Description |
FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
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| File Size |
707.21K /
89 Page |
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it Online |
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QuickLogic Corporation
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| Part No. |
QL3025
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| OCR Text |
pld Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
* 25,000 Usable pld Gates with 204 I/Os * 300 MHz www.DataSheet4U.com16-bit
Four Low-Skew Distributed Networks
* Tw... |
| Description |
pld Gate pASIC 3 FPGA Combining High Performance and High Density
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| File Size |
219.22K /
17 Page |
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it Online |
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st
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| Part No. |
DSM2180F3VNBSP
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| OCR Text |
...O controlled by DSP software or pld logic - 4mA I/O pin drive
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Content Security - Programmable Security Bit blocks access of device programmers and readers
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General purpose pld - Over 3,000 Gates of pld with 16 macro cells - Use... |
| Description |
1Mb Flash(3V), pld, up to 16 I/O
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| File Size |
488.82K /
63 Page |
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it Online |
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st
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| Part No. |
DSM2180F3
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| OCR Text |
...O controlled by DSP software or pld logic - 8mA I/O pin drive at 5 Vcc
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Content Security - Programmable Security Bit blocks access of device programmers and readers
s
General purpose pld - Over 3,000 Gates of pld with 16 macro ce... |
| Description |
1Mb Flash(5V), pld, up to 16 I/O
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| File Size |
488.49K /
63 Page |
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it Online |
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Atmel
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| Part No. |
ATF16V8CZ
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| OCR Text |
...k diagram high- performance ee pld atf16v8cz rev. 0453f ? 08/99 pin configurations all pinouts top view pin name function clk clock i logic inputs i/o bidirectional buffers oe output enable vcc +5v supply tssop 1 2 3 4 5 6 7 8 9 10 20 19 1... |
| Description |
250 gate zero power electrically erasable pld, 20 pins, 5V
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| File Size |
323.32K /
12 Page |
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it Online |
Download Datasheet |
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Price and Availability
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