| Description |
High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 64K X 16 STANDARD SRAM, 20 ns, PDSO44
5 V 64K X 16 CMOS SRAM 54K的16 CMOS SRAM
5 V 64K X 16 CMOS SRAM 64K X 16 STANDARD SRAM, 12 ns, PDSO44
5 V 64K X 16 CMOS SRAM 64K X 16 STANDARD SRAM, 20 ns, PDSO44
5 V 64K X 16 CMOS SRAM 64K X 16 STANDARD SRAM, 10 ns, PDSO44
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
High Speed CMOS Logic Triple 3-Input AND Gates 14-PDIP -55 to 125
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
SRAM - 5V Fast Asynchronous
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