|
|
 |

Silicon Laboratories
|
Part No. |
SI5341
|
OCR Text |
... lvds, lvpecl, lvcmos, cml, and hcsl with programmable signal amplitude ? si5341: 4 input, 10 output, 64-qfn 9x9 mm ? si5340: 4 input, 4 output, 44-qfn 7x7 mm up to 10 output clocks out7 out6 out5 out1 out4 out3 out2 out0 si5340 si5341 i2c... |
Description |
Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator
|
File Size |
5,443.68K /
53 Page |
View
it Online |
Download Datasheet
|
|
|
 |
Pericom Semiconductor C...
|
Part No. |
PI6LC4820ZDE
|
OCR Text |
...ential (accepts: lvds, lvpecl, hcsl) 47 in+ input (diferential) frequency input pin, diferential (accepts: lvds, lvpecl, hcsl) 48 in_se in...lvcmos input electrical characteristics symbol parameters conditions min. ty p. max. units v ih inp... |
Description |
HiFlex Ethernet Network Clock Generator
|
File Size |
939.96K /
13 Page |
View
it Online |
Download Datasheet
|
|
|
 |
ICS
|
Part No. |
ICS83023I
|
OCR Text |
...ls: LVDS, LVPECL, LVHSTL, SSTL, hcsl * Maximum output frequency: 350MHz (typical) * Output skew: 60ps (maximum) * Part-to-part skew: 500ps (...lvcmos outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with... |
Description |
Dual 1-to-1, Differential-to-lvcmos Translator/Buffer. Industrial Temperature.
|
File Size |
68.81K /
12 Page |
View
it Online |
Download Datasheet
|
|
|
 |
Integrated Device Techn...
|
Part No. |
5P1103
|
OCR Text |
...rential i/os - lvpecl, lvds and hcsl ? input frequency ranges: ? lvcmos reference clock input (xin/ref) ? 1mhz to 200mhz ? lvds, lvpecl, hcsl diffe rential clock input (clkin, clkinb) ? 1mhz to 350mhz ? crystal frequency range: 8mhz to 40... |
Description |
Four banks of internal non-volatile in-system
|
File Size |
398.79K /
32 Page |
View
it Online |
Download Datasheet
|
|
|
 |
Integrated Device Techn...
|
Part No. |
9FGV0831CKLF
|
OCR Text |
...res ? 8 - 100mhz low-power (lp) hcsl dif pair ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? r... |
Description |
8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
|
File Size |
334.37K /
17 Page |
View
it Online |
Download Datasheet
|
|
|
 |
Integrated Device Techn...
|
Part No. |
9FGV0831
|
OCR Text |
...res ? 8 - 100mhz low-power (lp) hcsl dif pair ? 1 - 1.8v lvcmos ref output w/wake-on-lan (wol) support key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif phase jitter is pcie gen1-2-3 compliant ? r... |
Description |
Outputs can optionally be supplied from any voltage
|
File Size |
203.38K /
16 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|