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Cypress
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Part No. |
PLDC20RA10 C20RA10
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OCR Text |
...utput macrocell programmable as combinatorial or asynchronous D-type registered output Product-term control of register clock, reset and set and output enable Register preload and power-up reset Four data product terms per output macrocell ... |
Description |
Reprogrammable Asynchronous CMOS Logic Device From old datasheet system
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File Size |
372.06K /
13 Page |
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it Online |
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Xilinx
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Part No. |
XC9536XV DS053 XC9536XV-SERIES
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OCR Text |
...elay Product term 3-state delay combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output ... |
Description |
High-performance CPLD From old datasheet system
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File Size |
59.60K /
8 Page |
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N/A Altera Corp
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Part No. |
EPM7032SLC44-10 EPM7128ELC84-20 EPM7128ELC84-15 EPM7128ELC84-10P EPM7128ELC84-10 EPM7064SLI44-7
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OCR Text |
...odates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.
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Description |
MAX 7000 Programmable Logic Device COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC COMPLEX-EEPLD,128-CELL,15NS PROP DELAY,LDCC,84PIN,PLASTIC COMPLEX-EEPLD,128-CELL,20NS PROP DELAY,LDCC,84PIN,PLASTIC COMPLEX-EEPLD,32-CELL,10NS PROP DELAY,LDCC,44PIN,PLASTIC
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File Size |
436.37K /
62 Page |
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it Online |
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Altera
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Part No. |
EPM7128SLC84-10
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OCR Text |
...odates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times.
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Description |
IC,COMPLEX-EEPLD,128-CELL,10NS PROP DELAY,LDCC,84PIN,PLASTIC
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File Size |
473.32K /
66 Page |
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it Online |
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Lattice Semiconductor Corporation LATTICE[Lattice Semiconductor] http://
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Part No. |
ISPLSI1024 ISPLSI1024EA-200LT100 1024EA ISPLSI1024EA-100LT100 ISPLSI1024EA-125LT100 ISPLSI1024EA ISPLS1024-100LT100 ISPLS1024-200LT100
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OCR Text |
... can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the ... |
Description |
200 MHz in-system prommable high density PLD Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:120ohm RoHS Compliant: Yes In-System Programmable High Density PLD 100 MHz in-system prommable high density PLD
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File Size |
159.21K /
13 Page |
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it Online |
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lattice
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Part No. |
LC4128V-10T100I
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OCR Text |
...roviding a fast path for narrow combinatorial functions, and to the logic allocator. Table 3. Individual PT Steering
Product Term PTn PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic PT Logic PT Logic PT Logic PT Logic PT Single PT for XOR/OR Individua... |
Description |
IC,COMPLEX-EEPLD,128-CELL,10.5NS PROP DELAY,QFP,100PIN,PLASTIC
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File Size |
264.92K /
83 Page |
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it Online |
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Lattice Semiconductor Corp
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Part No. |
LC4256 LC4384V75T176C LC4512 LC4128 LC4064 LC4032
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OCR Text |
...roviding a fast path for narrow combinatorial functions, and to the logic allocator. Table 3. Individual PT Steering
Product Term PTn PTn+1 PTn+2 PTn+3 PTn+4 Logic Logic PT Logic PT Logic PT Logic PT Logic PT Single PT for XOR/OR Individua... |
Description |
IC,COMPLEX-EEPLD,256-CELL,3.8NS PROP DELAY,QFP,100PIN,PLASTIC IC,COMPLEX-EEPLD,384-CELL,10NS PROP DELAY,QFP,176PIN,PLASTIC IC,COMPLEX-EEPLD,512-CELL,4.5NS PROP DELAY,QFP,176PIN,PLASTIC System Programmable Super Fast High Density PLDs IC,COMPLEX-EEPLD,64-CELL,3.2NS PROP DELAY,QFP,100PIN,PLASTIC IC,COMPLEX-EEPLD,32-CELL,3.2NS PROP DELAY,TQFP,48PIN,PLASTIC
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File Size |
740.67K /
91 Page |
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it Online |
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Xilinx
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Part No. |
XC95144XL 95144XL XC95144XL-SERIES
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OCR Text |
...ate delay Internal Register and combinatorial Delays combinatorial logic propagation delay tPDI Register setup time tSUI Register hold time tHI tECSU Register clock enable setup time tECHO Register clock enable hold time Register clock to o... |
Description |
High Performance CPLD From old datasheet system Preliminary Product Specification
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File Size |
78.77K /
9 Page |
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it Online |
Download Datasheet |
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Price and Availability
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