| |
|
 |
Mosel Vitelic Corp MOSEL[Mosel Vitelic, Corp] Mosel Vitelic Corp
|
| Part No. |
V43644R04V V43644R04VCTG-10PC
|
| OCR Text |
...TG-10PC
4
3
64
4
R
0
4
V
C
T
G
-
10PC
-10PC 100MHz 2-2-2
GOLD TSOP COMPONENT REVISION LEVEL BLANK = B REV. C = C REV. WIDTH DEPTH 168 PIN UNBUFFERED DIMM X 16 COMPONENT LVTTL 4 BANKS REFRESH RATE 4... |
| Description |
3.3 VOLT 4M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE
|
| File Size |
54.66K /
11 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
IDT
|
| Part No. |
79RC32333
|
| OCR Text |
...-up. Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below. Output Clock Optional clock output. PCI Multiplexed Address/Data Bus Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the... |
| Description |
Integrated Communications Processor
|
| File Size |
390.48K /
28 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
IDT
|
| Part No. |
79RC32334
|
| OCR Text |
...tion of Table 1, changed cpu_dr_r_n pin from Input to Output. Updated document from Advance to Preliminary Information. June 15, 2000: In Table 1, switched assertion and de-assertion for debug_cpu_dma_n signal. In the AC Timing Characterist... |
| Description |
Integrated Communications Processor
|
| File Size |
506.06K /
30 Page |
View
it Online |
Download Datasheet
|
| |
|
 |
ICS
|
| Part No. |
ICS9148-08
|
| OCR Text |
...ts dummy Byte count
A(6:0) & R/W# D2(H)
B.
ACK
ACK
ACK
Then Byte 0, 1, 2, etc in sequence until STOP.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in ... |
| Description |
Single Chip, Aladdin IV Clock with up to 83.3MHz From old datasheet system
|
| File Size |
581.27K /
14 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|