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ICS
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| Part No. |
ICS85211I-01
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| OCR Text |
...wing differential input levels: lvds, lvpecl, hstl, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any single-ended input signal to hstl levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: ... |
| Description |
Low-Skew, 1-to-2, Differential-to- hstl Fanout Buffer. VOHmax=1.4V. Industrial Temperature.
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| File Size |
94.63K /
13 Page |
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Download Datasheet
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
ICS8524AYLFT ICS8524AYT ICS8524AYLF
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| OCR Text |
...ferential input levels: lvpecl, lvds, hstl, SSTL, HCSL * PCLK, nPCLK supports the following input types: lvpecl, CML, SSTL * Maximum output frequency: 500MHz * Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to hstl levels wit... |
| Description |
LOW SKEW CLOCK DRIVER, 22 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-hstl FANOUT BUFFER
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| File Size |
184.43K /
17 Page |
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it Online |
Download Datasheet |
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Xilinx, Inc.
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| Part No. |
XCV812E-6FGG900C XCV812E-7FGG900C XCV812E-6FGG900I
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| OCR Text |
...rch 14, 2003 4 1-800-255-7778 r lvds dc specifications lvpecl dc specifications these values are valid at the output of the source termination pack shown under lv pe c l , with a 100 ? differential load only. the v oh levels are 200 mv b... |
| Description |
XCV812E-6FGG900C - NOT RECOMMENDED for NEW DESIGN FPGA, 4704 CLBS, 254016 GATES, 357 MHz, PBGA900
XCV812E-7FGG900C - NOT RECOMMENDED for NEW DESIGN FPGA, 4704 CLBS, 254016 GATES, 400 MHz, PBGA900
XCV812E-6FGG900I - NOT RECOMMENDED for NEW DESIGN FPGA, 4704 CLBS, 254016 GATES, 357 MHz, PBGA900
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| File Size |
172.94K /
20 Page |
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it Online |
Download Datasheet |
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