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| Part No. |
HYMD1166458
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| OCR Text |
...nced to both rising and falling edges of differential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data strobes and write data masks inputs are sampled on both rising and falling e... |
| Description |
16Mx64|2.5V|H/L|x8|DDR SDRAM - Unbuffered DIMM 128MB
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| File Size |
150.62K /
16 Page |
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NANOAMP[NanoAmp Solutions, Inc.]
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| Part No. |
NT5DS4M32EG-6 NT5DS4M32EG NT5DS4M32EG-5 NT5DS4M32EG-5G
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| OCR Text |
...ansactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Features... |
| Description |
1M 】 32 Bits 】 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
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| File Size |
781.03K /
46 Page |
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Pericom Technology
PERICOM[Pericom Semiconductor Corporation]
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| Part No. |
PI6C2410QE PI6C2410 PI6C2410L PI6C2410LE PI6C2410Q
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| OCR Text |
...2.0V 35 50 CLKIN to FBIN rising edges @VDD/2 @1.4V, rising edges @VDD/2, rising edges, same CLKIN -150 40 66 80 160 150 200 400 200 65 1. 5 % ns ps MHz Te s t Conditions Low Freq., HF# = "1" M in. 10 Typ. 33 M ax. 40 Units
Note: Tjc = Tp... |
| Description |
PCI-X Clock Buffers
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| File Size |
82.89K /
6 Page |
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ALSC[Alliance Semiconductor Corporation]
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| Part No. |
AS80M2516A AS80M2516A_V1.0
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| OCR Text |
...) to one clock period On rising edges 500 s apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT =
CLOCK (MHz)
MIN
TYP
MAX
UNIT
fo tr Tf
4 2.1 1.9
140
MHz ns ns
Clock Outputs (PLL A clock v... |
| Description |
3.3 V, generater an EMI optimizer clocking signal at output
dual phase lock loop clock chip
From old datasheet system
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| File Size |
437.78K /
15 Page |
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Nanya Techology
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| Part No. |
NT5DS32M8BF NT5DS64M4BT
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| OCR Text |
...d data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? 7.8 m s maximum average periodic refresh interval ? sstl_2... |
| Description |
(NT5DSxxMxBx) 256Mb DDR SDRAM
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| File Size |
1,953.01K /
80 Page |
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Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
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| Part No. |
AS7C3364PFS36A-166TQI AS7C3364PFS32A AS7C3364PFS32A-100TQC AS7C3364PFS32A-100TQI AS7C3364PFS32A-133TQC AS7C3364PFS32A-133TQI AS7C3364PFS32A-150TQC AS7C3364PFS32A-150TQI AS7C3364PFS32A-166TQC AS7C3364PFS32A-166TQI AS7C3364PFS36A AS7C3364PFS36A-100TQC AS7C3364PFS36A-100TQI AS7C3364PFS36A-133TQC AS7C3364PFS36A-133TQI AS7C3364PFS36A-150TQC AS7C3364PFS36A-150TQI AS7C3364PFS36A-166TQC
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...sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst operation is selectable with the LBO input. With LBO unconnected or ... |
| Description |
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 9 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 36 STANDARD SRAM, 10 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 10 ns, PQFP100
DIODE ZENER SINGLE 1000mW 16Vz 15.5mA-Izt 0.05 5uA-Ir 12.2Vr DO41-GLASS 5K/REEL 64K X 36 STANDARD SRAM, 12 ns, PQFP100
3.3V 64K X 32/36 pipeline burst synchronous SRAM 64K X 32 STANDARD SRAM, 12 ns, PQFP100
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| File Size |
216.30K /
11 Page |
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| Part No. |
K7A403600M-TC11
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| OCR Text |
...zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. the accesses are enabled with the chip select signals and output enabled signals. wait states... |
| Description |
128K X 36 CACHE SRAM, 4 ns, PQFP100
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| File Size |
406.29K /
15 Page |
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Price and Availability
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