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Zarlink Semiconductor Inc.
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| Part No. |
MT9046 MT9046AN
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the device has reference switching and frequency holdover capabilities to help maintain conn... |
| Description |
T1/E1 System Synchronizer with Holdover
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| File Size |
307.19K /
34 Page |
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zarlink
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| Part No. |
ZL30102
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| OCR Text |
...Circuit
Virtual Reference
DPLL
Mode Control
E1 Synthesizer
C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o F16o C1.5o C3o C6o
DS1 Synthesizer DS2 Synthesizer Frequency Select MUX IEEE 1149.1a
TRST
MODE_SEL1:0 SEC_MSTR
HMS ... |
| Description |
Stratum 4/4E Redundant System Clock Synchronizer for T1/E1 and H.110
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| File Size |
385.42K /
47 Page |
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it Online |
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zarlink
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| Part No. |
ZL30106
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| OCR Text |
DPLL
Data Sheet Features
* * Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces Accepts three input re... |
| Description |
SONET/SDH/PDH Network Interface DPLL
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| File Size |
395.38K /
46 Page |
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it Online |
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Zarlink
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| Part No. |
ZL30409
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| OCR Text |
...ns a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.4... |
| Description |
T1/E1 System Synchronizer with Stratum 3 Holdover
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| File Size |
277.95K /
32 Page |
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it Online |
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IDT
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| Part No. |
IDT82V3011
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| OCR Text |
...Control Block Virtual Reference DPLL C3o C1.5o C6o F0o F8o MON_out Reference Input Monitor Invalid Input Signal Detection F16o F19o F32o RSP TSP LOCK
Fref
Feedback Signal
State Control Circuit
Input Frequency Selection
TIE_en... |
| Description |
T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
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| File Size |
345.92K /
30 Page |
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it Online |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
MT9045AN MT9045
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| OCR Text |
...or Circuit
Virtual Reference DPLL Output Interface Circuit
Reference Select MUX Reference Monitor
Selected Reference TIE Corrector Enable Reference Select
State Select Input Impairment Monitor
State Select
C19o C1.5o C2o C... |
| Description |
Dual reference frequency selectable 3.3V Digital PLL with multiple clock outputs for T1/E1 (ITU-T G.812 type IV), Stratum( 3, 4, 4E) and STS-3/OC3 systems
T1/E1/OC3 System Synchronizer
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| File Size |
292.25K /
34 Page |
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it Online |
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Zarlink Semiconductor Inc.
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| Part No. |
ZL50022QCC
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| OCR Text |
...ated digital phase-locked loop (dpll) exceeds telcordia gr-1244-core stratum 4e specifications ? output clocks have less than 1 ns of jitter (except for the 1.544 mhz output) ? dpll provides holdover, freerun and jitter attenuation feat... |
| Description |
Enhanced 4 K Digital Switch with Stratum 4E DPLL
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| File Size |
936.51K /
121 Page |
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it Online |
Download Datasheet |
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Price and Availability
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