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Samsung Electronic
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| Part No. |
S5L9290X02
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| OCR Text |
... processing, wide capture range dpll and 1-bit dac for the internet audio cd player are installed in s5l9290x02. features ? signal processing part ? efm data demodulation ? frame sync detection, protection, insertion ? sub code data proces... |
| Description |
DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO
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| File Size |
200.82K /
47 Page |
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zarlink
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| Part No. |
ZL30102
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| OCR Text |
...Circuit
Virtual Reference
dpll
Mode Control
E1 Synthesizer
C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o F16o C1.5o C3o C6o
DS1 Synthesizer DS2 Synthesizer Frequency Select MUX IEEE 1149.1a
TRST
MODE_SEL1:0 SEC_MSTR
HMS ... |
| Description |
Stratum 4/4E Redundant System Clock Synchronizer for T1/E1 and H.110
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| File Size |
385.42K /
47 Page |
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it Online |
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zarlink
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| Part No. |
ZL30106
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| OCR Text |
dpll
Data Sheet Features
* * Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces Accepts three input re... |
| Description |
SONET/SDH/PDH Network Interface dpll
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| File Size |
395.38K /
46 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
ZL30409
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The ZL30409 generates ST-BUS clock and framing signals that are phase locked to either a 19.4... |
| Description |
T1/E1 System Synchronizer with Stratum 3 Holdover
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| File Size |
277.95K /
32 Page |
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it Online |
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IDT
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| Part No. |
IDT82V3011
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| OCR Text |
...Control Block Virtual Reference dpll C3o C1.5o C6o F0o F8o MON_out Reference Input Monitor Invalid Input Signal Detection F16o F19o F32o RSP TSP LOCK
Fref
Feedback Signal
State Control Circuit
Input Frequency Selection
TIE_en... |
| Description |
T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
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| File Size |
345.92K /
30 Page |
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it Online |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
MT9045AN MT9045
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| OCR Text |
...or Circuit
Virtual Reference dpll Output Interface Circuit
Reference Select MUX Reference Monitor
Selected Reference TIE Corrector Enable Reference Select
State Select Input Impairment Monitor
State Select
C19o C1.5o C2o C... |
| Description |
Dual reference frequency selectable 3.3V Digital PLL with multiple clock outputs for T1/E1 (ITU-T G.812 type IV), Stratum( 3, 4, 4E) and STS-3/OC3 systems
T1/E1/OC3 System Synchronizer
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| File Size |
292.25K /
34 Page |
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it Online |
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Maxim Integrated Products, Inc.
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| Part No. |
DS3104
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| OCR Text |
... iming c ard to l ine c ard dpll f eatures (t0 dpll).............................................................. 11 5.3 l ine c ard to t iming c ard dpll f eatures (t4 dpll)...................................................... |
| Description |
Line Card Timing IC with Synchronous Ethernet Support 线卡时钟IC，支持同步以太网
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| File Size |
686.74K /
135 Page |
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it Online |
Download Datasheet |
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Price and Availability
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