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Integrated Device Technology, Inc.
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Part No. |
ICS9FG107 ICS9FG107YFLFT ICS9FG107YFLNT
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OCR Text |
...put for enabling output 6. 0 = tri-state outputs, 1= enable outputs 12 dif_6 out 0.7v differential true clock output 13 dif_6# out 0.7v dif...mode. this input is not latched at power up. 0 = down spread, 1 = center spread 46 iref out this ... |
Description |
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
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File Size |
229.44K /
18 Page |
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