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STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
74LVX373TTR 74LVX373 74LVX373M 74LVX373MTR
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| OCR Text |
...puts will follow the data input precisely. PIN CONNECTION AND IEC LOGIC SYMBOLS
When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a... |
| Description |
低电压CMOS八进制D型锁存器（三态非刑事调查。容限为5V输入
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS
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| File Size |
68.56K /
10 Page |
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ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
74LVQ573T 74LVQ573 74LVQ573M 4909
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| OCR Text |
...puts will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic l... |
| Description |
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
From old datasheet system
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| File Size |
73.98K /
10 Page |
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it Online |
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STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
74LVQ373T 74LVQ373 74LVQ373M
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| OCR Text |
...puts will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic l... |
| Description |
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
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| File Size |
73.88K /
10 Page |
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it Online |
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STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
74LVC573ATTR 74LVC573A 74LVC573AMTR
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| OCR Text |
...puts will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic ... |
| Description |
OCTAL D-TYPE LATCH HIGH PERFORMANCE
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| File Size |
170.68K /
13 Page |
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it Online |
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STMicroelectronics N.V.
STMICROELECTRONICS[STMicroelectronics]
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| Part No. |
74LCX16373TTR 74LCX16373
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| OCR Text |
...puts will follow the data input precisely. When the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low log... |
| Description |
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH(3-STATE)WITH 5V TOLERANT INPUTS AND OUTPUTS 低电压CMOS 16位D型锁存器 -国家与承V的输入和输出
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| File Size |
66.82K /
9 Page |
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it Online |
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