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  lvds lvpecl hstl Datasheet PDF File

For lvds lvpecl hstl Found Datasheets File :: 394    Search Time::2.11ms    
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    ICS
Part No. ICS8521I
OCR Text ...ferential input levels: lvpecl, lvds, hstl, SSTL, HCSL * PCLK, nPCLK supports the following input types: lvpecl, CML, SSTL * Maximum output frequency: 500MHz * Output skew: 25ps (typical) * Part-to-part skew: 200ps (typical) * Propagation d...
Description Low Skew, 1-to-9, Differential-to- hstl Fanout Buffer. Industrial Temp. VOHmax=1.4V. (P)

File Size 115.29K  /  14 Page

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    SILICONLABORATORIES-SI5334B-A00124-GMR SI5334C-A00136-GM

SILICON LABORATORIES
Part No. SILICONLABORATORIES-SI5334B-A00124-GMR SI5334C-A00136-GM
OCR Text ...y frequency or format ?? lvpecl/lvds: 0.16 to 710 mhz ?? hcsl: 0.16 to 250 mhz ?? cmos: 0.16 to 200 mhz ?? sstl/hstl: 0.16 to 350 mhz ? independent output voltage per driver ?? 1.5, 1.8, 2.5, or 3.3 v ? independent core supply voltage ?? 1...
Description PLL BASED CLOCK DRIVER, QCC24

File Size 205.02K  /  34 Page

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    Xilinx, Inc.
XILINX INC
Part No. XCV100E-6BGG352I XCV100E-6BGG352C XCV300E-8BG432I XCV300E-7FG456C XCV1000E-6FGG680C XCV300E-6BGG352C XCV200E-7CSG144I XCV50E-6PQG240C XCV400E-6PQG240I XCV300E-7BGG352C XCV1600E-6FGG1156C XCV1000E-8FGG1156C XCV600E-8BGG560I XCV1600E-8BGG560C XCV1000E-8BGG560I
OCR Text ...pci66_3 3.3 3.3 n/a n/a blvds & lvds 2.5 n/a n/a n/a lvpecl 3.3 n/a n/a n/a virtex?-e 1.8 v field programmable gate arrays r ds022-2 (v2.8) january 16, 2006 www.xilinx.com module 2 of 4 production product specification 3 eight i/o banks r...
Description XCV100E-6BGG352I - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 32400 GATES, 357 MHz, PBGA352
XCV100E-6BGG352C - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 32400 GATES, 357 MHz, PBGA352
Virtex-E 1.8 V Field Programmable Gate Arrays FPGA, 1536 CLBS, 82944 GATES, 416 MHz, PBGA432
Virtex-E 1.8 V Field Programmable Gate Arrays FPGA, 1536 CLBS, 82944 GATES, 400 MHz, PBGA456
FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN FPGA, 6144 CLBS, 331776 GATES, 357 MHz, PBGA680
300,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN FPGA, 1536 CLBS, 82944 GATES, 357 MHz, PBGA352
XCV200E-7CSG144I - NOT RECOMMENDED for NEW DESIGN FPGA, 1176 CLBS, 63504 GATES, 400 MHz, PBGA144
XCV50E-6PQG240C - NOT RECOMMENDED for NEW DESIGN FPGA, 384 CLBS, 20736 GATES, 357 MHz, PQFP240
XCV400E-6PQG240I - NOT RECOMMENDED for NEW DESIGN FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PQFP240
XCV300E-7BGG352C - NOT RECOMMENDED for NEW DESIGN FPGA, 1536 CLBS, 82944 GATES, 400 MHz, PBGA352
XCV1600E-6FGG1156C - NOT RECOMMENDED for NEW DESIGN FPGA, 7776 CLBS, 419904 GATES, 357 MHz, PBGA1156
XCV1000E-8FGG1156C - NOT RECOMMENDED for NEW DESIGN FPGA, 6144 CLBS, 331776 GATES, 416 MHz, PBGA1156
FPGA, 3456 CLBS, 186624 GATES, 416 MHz, PBGA560
FPGA, 7776 CLBS, 419904 GATES, 416 MHz, PBGA560
FPGA, 6144 CLBS, 331776 GATES, 416 MHz, PBGA560

File Size 503.05K  /  54 Page

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    PO74HSTL85331A PO74HSTL85331ATR PO74HSTL85331ATU

Potato Semiconductor Corporation
Part No. PO74hstl85331A PO74hstl85331ATR PO74hstl85331ATU
OCR Text ...ferential input levels: lvpecl, lvds, LVhstl, SSTL, HCSL . Operating frequency up to 700MHz with 2pf load . Operating frequency up to 550MHz with 5pf load . Operating frequency up to 400MHz with 15pf load . Very low output pin to pin skew <...
Description 3.3V 1:4 Crystal Oscillator/ Differential Clock or Data Fanout Buffer

File Size 669.38K  /  8 Page

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    MC100LVEP14-D

ON Semiconductor
Part No. MC100LVEP14-D
OCR Text ...ith v ee = 2.375 v to 3.8 v ? lvds input compatible ? open input default state http://onsemi.com device package shipping ordering informat...lvpecl /hstl maximum frequency (see figure 2. f max /jitter) > 2 > 2 > 2 ghz t plh t phl propagation...
Description 2.5V / 3.3V 1:5 Differential ECL/PECL/hstl Clock Driver

File Size 67.25K  /  8 Page

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    NB6L14MNG NB6L14MNR2G NB6L14

ONSEMI[ON Semiconductor]
Part No. NB6L14MNG NB6L14MNR2G NB6L14
OCR Text ... lvpecl, LVCMOS, LVTTL, CML, or lvds logic levels. The VREF_AC reference output can be used to rebias capacitor-coupled differential or sing...lvpecl Outputs, 720 mV Amplitude, Typical lvpecl Mode Operating Range: VCC = 2.375 V to 3.63 V with ...
Description 2.5 V/3.3 V 3.0 GHz Differential 1:4 lvpecl Fanout Buffer

File Size 145.31K  /  10 Page

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    ALTERA[Altera Corporation]
Part No. EP20K200EXXXX EP20K200XXXX EP20K200EBC652 EP20K200E EP20K200 EP20K160E EP20K160EXXXX EP20K30E EP20K30EXXXX APEX20K EP20K600E EP20K1000E EP20K1500E EP20K60E EP20K100 EP20K100E EP20K300E EP20K400 EP20K400E
OCR Text ...nce (tCO + tSU) up to 250 MHz - lvds performance up to 840 Mbits per channel - Direct connection from I/O pins to local interconnect providi...lvpecl, PCI-X, AGP, CTT, stubseries terminated logic (SSTL-3 and SSTL-2), Gunning transceiver logic ...
Description (APEP20K Series) Programmable Logic Device Family

File Size 604.10K  /  117 Page

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    SY89871U07 SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR

Micrel Semiconductor
Part No. SY89871U07 SY89871UMG SY89871UMGTR SY89871UMI SY89871UMITR
OCR Text ...ny differential inputs (lvpecl, lvds, CML, hstl) TTL/CMOS inputs for select and reset 100K EP compatible lvpecl outputs Parallel programming capability Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) pa...
Description 2.5GHz ANY DIFF. IN-TO-lvpecl PROGRAMMABLE CLOCK DIVIDER

File Size 155.05K  /  10 Page

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    ONSEMI[ON Semiconductor]
Part No. NB6L14MNG NB6L14_07 NB6L14 NB6L14MNR2G
OCR Text ... lvpecl, LVCMOS, LVTTL, CML, or lvds logic levels. The VREF_AC reference output can be used to rebias capacitor-coupled differential or sing...lvpecl Outputs, 700 mV Amplitude, Typical lvpecl Mode Operating Range: VCC = 2.375 V to 3.63 V with ...
Description 2.5 V/3.3 V 3.0 GHz Differential 1:4 lvpecl Fanout Buffer

File Size 110.34K  /  10 Page

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    SY89872UMI SY89872UMITR SY89872UMG SY89872UMGTR SY89872U

MICREL[Micrel Semiconductor]
Part No. SY89872UMI SY89872UMITR SY89872UMG SY89872UMGTR SY89872U
OCR Text lvds SY89872U (R) PROGRAMMABLE CLOCK DIVIDER/FANOUT Precision Edge SY89872U BUFFER WITH INTERNAL TERMINATION (R) FEATURES Guaranteed...lvpecl, lvds, CML, hstl) Precision differential lvds outputs Matched delay: all outputs have match...
Description 2.5V, 2GHz ANY DIFF. IN-TO-lvds PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

File Size 561.07K  /  10 Page

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For lvds lvpecl hstl Found Datasheets File :: 394    Search Time::2.11ms    
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