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hcsl lvds Datasheet PDF File

For hcsl lvds Found Datasheets File :: 529 Search Time::2.484ms
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				Integrated Device Technology
Part No.	5V19EE901NLGI 5V19EE901PGGI 5V19EE901PGGI8 5V19EE901NLGI8 IDT5V19EE901
OCR Text	...support lvttl, lvpecl, lvds or hcsl logic levels. out0 (output 0) supports 3.3v single ended output only. the outputs are connected to the plls via a switch matrix. the switch matrix allows the user to route the pll outputs to any outp...
Description	EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
File Size	495.07K / 35 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	ICS557-01
OCR Text	...mhz crystal input and produces hcsl (host clock signal level) differential outputs at 100 mhz clock frequency. lvds signal levels can also be supported via an alternative termination scheme. features ? supports pci-express tm hcsl outpu...
Description	PCI-EXPRESS GEN1 CLOCK SOURCE
File Size	115.30K / 10 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	5V49EE501NLGI 5V49EE501NLGI8
OCR Text	...support lvttl, lvpecl, lvds or hcsl logic levels. out0 (output 0) supports 3.3v single ended output only. the outputs are connected to the plls via a switch matrix. the switch matrix allows the user to route the pll outputs to any outp...
Description	5V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC24 4 X 4 MM, ROHS COMPLIANT, VFQFPN-24
File Size	283.96K / 33 Page	View it Online	Download Datasheet

				Pericom Semiconductor Corporation
Part No.	PI6C557-03AQE PI6C557-03ALE PI6C557-03ALEX
OCR Text	...a provides two diferential (hcsl) or lvds spread spectrum outputs. te pi6c557-03a is confgured to se - lect spread and clock selection. using pericom's patented phase- locked loop (pll) techniques, the device takes a 25mhz crystal i...
Description	PCIe 2.0 Clock Generator with 2 hcsl Outputs
File Size	696.58K / 9 Page	View it Online	Download Datasheet

				Epson ToYoCom, Corp.
Part No.	EG-2121CA166.6286M-PGPAL0 EG-2121CA166.6286M-LGPAL0
OCR Text	...differential lv-pecl or lvds or hcsl ? function : output enable(oe) ? external dimensions : 7.0 5.0 1.2 t (mm) typ. ? very low jitter and low phase noise by saw unit. product number (please contact us) eg-2 1 2 1 c...
Description	CLOCK SAW OSCILLATOR, 166.6286 MHz ROHS COMPLIANT, CERAMIC PACKAGE-6
File Size	687.68K / 3 Page	View it Online	Download Datasheet

				Integrated Circuit Systems
Part No.	ICS557-08 ICS557G-08 ICS557G-08LF ICS557G-08LFT ICS557G-08T ICS557GI-08 ICS557GI-08LF ICS557GI-08LFT ICS557GI-08T
OCR Text	...e user to select one of the two hcsl (Host Clock Signal Level) or lvds input pairs and fan out to one pair of differential hcsl or lvds outputs. This chip is suited especially for PCI-Express applications, where there is a need to select th...
Description	2:1 MULTIPLEXER CHIP FOR PCI-EXPRESS
File Size	175.83K / 11 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB4N111KMNR4G NB4N111KMNG
OCR Text	...ential fanout clock driver with hcsl level output description the nb4n111k is a differential input clock 1 to 10 hcsl fanout buffer, optimiz...lvds levels. single ? ended lvpecl, cml, lvcmos or lvttl levels are accepted with the proper v refac...
Description	3.3V Differential In 1:10 Differential Fanout Clock Driver with hcsl Level Output
File Size	124.54K / 10 Page	View it Online	Download Datasheet

				Micrel Semiconductor
Part No.	SM803020 SM803020UMY SM803020UMYR A18 B20 B12 A44
OCR Text	... to a differential pecl, lvds, hcsl , or cmos output logic level. pecl is selected by default, but can be overridden through spi. it is packaged in a dual - row 84 - pin 7 mm x 7mm pac kage. datasheets and support documentat...
Description	Flexible Ultra-Low Jitter Clock Synthesizer Flexible Ultra-Low Jitter Clock Synthesizer
File Size	883.19K / 14 Page	View it Online	Download Datasheet

				Integrated Device Technology Integrated Device Techn...
Part No.	ICS854104
OCR Text	... levels: lvpecl, lvds, lvhstl, hcsl, sstl ? each output has an individual oe control ? maximum output frequency: 700mhz ? translates differential input signals to lvds levels ? additive phase jitter, rms: 0.232ps (typical) ? output skew: 5...
Description	Low Skew, 1-to-4, Differential-to-lvds Fanout Buffer
File Size	690.19K / 15 Page	View it Online	Download Datasheet

For hcsl lvds Found Datasheets File :: 529 Search Time::2.484ms
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