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For clocks Found Datasheets File :: 21309    Search Time::1.281ms    
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    HYS72D64301HBR07

Qimonda AG
Part No. HYS72D64301HBR07
OCR Text ...25331" means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), SPD code definition version 1, and the Raw Card used for this module. TABLE 3 Address Format Density 512 MB 1 GB...
Description 184-Pin Registered Double-Data-Rate SDRAM Module

File Size 1,240.82K  /  39 Page

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    R4430PCF10MCM R4430SC1MF10MCM R4400 R4400PC R4400SC R4430PCP10MCM R4400MC R440. R440.PC R440.SC

AEROFLEX[Aeroflex Circuit Technology]
Aeroflex Inc.
Aeroflex, Inc.
Part No. R4430PCF10MCM R4430SC1MF10MCM R4400 R4400PC R4400SC R4430PCP10MCM R4400MC R440. R440.PC R440.SC
OCR Text ...rout SyncOut O O I O O Transmit clocks : Two identical transmit clocks that establish the system interface frequency Receive clocks: Two identical receive clocks that establish the system interface frequency Master clock: Master clock input...
Description The Aeroflex RISC TurboEngine Microprocessor Multichip Module
A MIPS R4400 RISC Microprocessor Multichip Module 基于MIPS R4400 RISC微处理器的多芯片模块

File Size 169.13K  /  11 Page

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    EMMICRO[EM Microelectronic - MARIN SA]
Part No. EM6522
OCR Text ...rge Voltage range, 2 to 5.5 V 2 clocks per instruction cycle 72 basic instructions EEPROM 4096 x 16 bits RAM 128 x 4 bits Max. 12 inputs ; port A, port B, port SP Max. 8 outputs ; port B, port SP Voltage Level Detector, 8 levels software se...
Description MFP version of EM6622 Ultra Low Power Microcontroller with 4x32 LCD Driver

File Size 1,149.67K  /  68 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY7C1522KV18-250BZI CY7C1529KV18-300BZXI CY7C1529KV18-167BZXC
OCR Text ...666 mhz) at 333 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for output data (c and c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data c...
Description 8M X 8 DDR SRAM, 0.45 ns, PBGA165
8M X 9 DDR SRAM, 0.45 ns, PBGA165
8M X 9 DDR SRAM, 0.5 ns, PBGA165

File Size 591.02K  /  32 Page

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    IDT
Part No. IDT71P71104 IDT71P71204
OCR Text ...on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. all interfaces of the ddrii sram are hstl, allowing speeds be- yond sram devices that use any form of ttl interface. the interfa...
Description 1.8V 2M x 9 DDR II Pipelined SRAM
1.8V 2M x 8 DDR II Pipelined SRAM

File Size 612.62K  /  24 Page

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    ISPLSI3448-90LB432 ISPLSI3448-70LB432 ISPLSI3448

Lattice Semiconductor
Part No. ISPLSI3448-90LB432 ISPLSI3448-70LB432 ISPLSI3448
OCR Text ...-- Synchronous and Asynchronous clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible I/O Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AN...
Description Electrically-Erasable Complex PLD
In-System Programmable High Density PLD

File Size 169.32K  /  14 Page

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    CYPRESS
Part No. CY28441
OCR Text ...airs * 100-MHz differential SRC clocks * 96-MHz differential dot clock * 48-MHz USB clocks * SRC clocks independently stoppable through CLKREQ#[A:B] * 33-MHz PCI clock * Low-voltage frequency select input * I2C support with readback capabil...
Description Clock Generator for Intel® Alviso Chipset

File Size 264.69K  /  21 Page

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    MAX124607 MAX1247CCEE MAX1247CEEE

Maxim Integrated Products
Part No. MAX124607 MAX1247CCEE MAX1247CEEE
OCR Text ...rnal clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1246--4.7F capacitor at VREF pin; MAX1247--external reference, VREF = 2.5V applied to VREF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1...
Description 2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

File Size 346.11K  /  26 Page

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    AK5357ET AK5357 AK5357VT AKD5357

Asahi Kasei Microsystem...
Asahi Kasei Microsystems
Part No. AK5357ET AK5357 AK5357VT AKD5357
OCR Text ...84fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock fre...
Description 24Bit 96kHz ツヒ ADC
24Bit 96kHz ΔΣ ADC

File Size 126.78K  /  19 Page

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