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Infineon
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| Part No. |
AP1601 AP160102
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| OCR Text |
...ed radix point is located right behind the sign bit. Supposing we perform a signed multiplication the result will be a 32 bit signed number stored in the register pair of the multiply and divide unit, MDL and MDH. After the multiplication h... |
| Description |
Biquad IIR Filter - C166 Family with Signal Processing Capabilities
From old datasheet system
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| File Size |
92.11K /
9 Page |
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MITSUBISHI[Mitsubishi Electric Semiconductor]
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| Part No. |
M64898GP M64898E
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| OCR Text |
... state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. Lock detector output. When loop of phase locked loop locked it, it rises with "H" level in "L" l... |
| Description |
From old datasheet system
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
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| File Size |
60.49K /
8 Page |
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SIEMENS[Siemens Semiconductor Group]
Infineon
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| Part No. |
TDA4390-2X TDA43902 Q67000-A5183
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| OCR Text |
...An input level switch circuitry behind the input switch realizes the adaption of different signal source levels. A gain of 0 dB or 6 dB is possible. After this section a stereo output/input is placed for connecting external circuits like an... |
| Description |
From old datasheet system
Audioprocessor
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| File Size |
921.30K /
39 Page |
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it Online |
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MAXIM - Dallas Semiconductor
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| Part No. |
DS9092GT DS9092 9092 DS9092T
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| OCR Text |
...panel-mount probes are fastened behind the panel with a push-on type spring nut. The two 15 cm 22AWG wires are provided for easy connection to the system microcontroller. The handgrip mount probe comes attached to a 10 cm handle and 1-meter... |
| Description |
iButton Probe
iButtonTM Probe
From old datasheet system
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| File Size |
76.25K /
2 Page |
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it Online |
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Zarlink
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| Part No. |
MT8941B 119
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| OCR Text |
...als. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is... |
| Description |
Advanced T1/CEPT Digital Trunk PLL
From old datasheet system
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| File Size |
604.46K /
29 Page |
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it Online |
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Zarlink
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| Part No. |
MT8940 118
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| OCR Text |
...als. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is... |
| Description |
ISO-CMOS ST-BUS? FAMILY
From old datasheet system
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| File Size |
492.69K /
19 Page |
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it Online |
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