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Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
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| Part No. |
LFE3-95EA-6FN672C LFE3-95EA-8FN672C LFE3-150EA-7FN672ITW LFE3-95E-7FN1156C LFE3-70E-8FN1156I LFE3-70EA-8FN484I LFE3-150EA-6FN672ITW LFE3-150EA-8FN672CTW LFE3-150EA-6FN1156C LFE3-35EA-7FTN256I
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| OCR Text |
...nfigured to support an array of popular data protocols including pci express, smpte, ethernet (xaui, gbe, and sgmii) and cpri. transmit pre-empha- sis and receive equalization settings make the serdes suitable for transmission and receptio... |
| Description |
FPGA, 375 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
FPGA, 500 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
FPGA, 420 MHz, PBGA672 27 X 27 MM, LEAD FREE, FPBGA-672
Field Programmable Gate Arrays - FPGAs 92K LUTs, 490 I/O 7 Speed FPGA, 420 MHz, PBGA1156
Field Programmable Gate Arrays - FPGAs 66.5K LUTs, 490 I/O 8 Speed FPGA, 500 MHz, PBGA1156
FPGA, 500 MHz, PBGA484 23 X 23 MM, LEAD FREE, FPBGA-484
FPGA, 375 MHz, PBGA1156
FPGA, PBGA256
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| File Size |
2,549.28K /
130 Page |
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it Online |
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Intersil, Corp.
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| Part No. |
X68C64SLIC
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| OCR Text |
...ss/data bus direct interface to popular 68hc11 family ? block protect register individually set write lock out in 1k blocks ? toggle bit polling early end of write detection ? page mode write allows up to 32 bytes to be written in one writ... |
| Description |
EE Micro-Peripheral(多重地址/数据总线，高速CMOS,微控制器外围芯片) 电子工程专辑微周边（多重地址/数据总线，高速的CMOS微控制器外围芯片
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| File Size |
85.53K /
4 Page |
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it Online |
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Maxim Integrated Products, Inc.
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| Part No. |
DS38464-070
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| OCR Text |
...nge of 3.0v to 3.6v employs popular jedec standard 72- position simm connector operating temperature: 0 o c to +70 o c pin description a0 - a15 - address inputs dq0 ? dq39 - data inputs/outputs cea\ - chip enable inputs we\ - wr... |
| Description |
3.3V 64k x 40 NV SRAM SIMM 64K X 40 NON-VOLATILE SRAM MODULE, 70 ns, SMA72
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| File Size |
220.63K /
11 Page |
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it Online |
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NEC, Corp.
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| Part No. |
EA-C10
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| OCR Text |
...h a range of options available, popular design synthesis tools are able to make the optimal size/performance/power choice for each path. all memory macros can be combined with a built-in-self- test (bist) macro for easy and high-performance... |
| Description |
CMOS Embedded Array (ASIC)(CMOS 嵌入式阵 嵌入式阵列（专用集成电路）的CMOS（嵌入式阵列的CMOS
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| File Size |
54.90K /
8 Page |
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it Online |
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