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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
9DBL411aKLF
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| OCR Text |
...express and cpu clocks 20-pin mlf or tssop packaging output features: 4 - low power differential output pairs individual oe# control of each output pair general description: the ics9dbl411 is a 4 output lower power differential buff... |
| Description |
LOW SKEW CLOCK DRIVER, PQCC20
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| File Size |
85.90K /
9 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
IDTCSPT857C
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| OCR Text |
... 48-pin TSSOP and TVSOP, 40-pin mlf, and 56-pin VFBGa packages
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9],... |
| Description |
2.5V - 2.6V PHaSE LOCKED LOOP DIFFERENTIaL 1:10 SDRaM CLOCK DRIVER
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| File Size |
135.63K /
15 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDTCSPU877
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| OCR Text |
...ble in 52-Ball VFBGa and 40-pin mlf packages
aPPLICaTIONS:
* Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver * along with SSTU32864/a, DDR2 register, provides complete solution for DDR2 DIMMs
The CSPU877 is a ... |
| Description |
1.8V PHaSE LOCKED LOOP DIFFERENTIaL 1:10 SDRaM CLOCK DRIVER
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| File Size |
136.73K /
13 Page |
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it Online |
Download Datasheet |
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Price and Availability
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