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PC121 XC6405E CJ2302S C5603 NTXV1N 472M03 89C51 MRF19085
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    CXD2064Q

Sony Corporation
Part No. CXD2064Q
OCR Text ...d. Clock input. Input the burst-locked fsc (2fsc) when using the internal PLL. Input the burst-locked 4fsc when not using the internal PLL. PLL control. Low: The internal PLL is not used. The clock (4fsc) which is input to FIN is supplied i...
Description Digital Comb Filter (NTSC/PAL)

File Size 264.56K  /  15 Page

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    CY2291 CY2291F CY2291FI CY2291SC-XXX CY2291SI-XXX CY2291SL-XXX

Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
CYPRESS[Cypress Semiconductor]
Part No. CY2291 CY2291F CY2291FI CY2291SC-XXX CY2291SI-XXX CY2291SL-XXX
OCR Text locked loops EPROM programmability Benefits Generates up to 3 custom frequencies from external sources Easy customization and fast turnaround Factory-programmable (CY2291) or field-programmable Programming support available for all oppor...
Description Three-PLL General Purpose EPROM Programmable Clock Generator 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20

File Size 120.66K  /  13 Page

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    DDP3310B

Micronas
ETC
Part No. DDP3310B
OCR Text ...cs General Characteristics Line-locked Clock Inputs: LLC1, LLC2 Luma, Chroma Inputs Reset Input, Test Input Half-Contrast Input I2C-Bus Interface Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins Horizontal Flyback Inpu...
Description Display and Deflection Processor

File Size 1,011.92K  /  60 Page

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    DS21552L DS21552LN DS21352 DS21352L DS21352LN

DALLAS[Dallas Semiconductor]
DALLAS[Dallas Semiconducotr]
Part No. DS21552L DS21552LN DS21352 DS21352L DS21352LN
OCR Text ... 8.192MHz 8.192MHz clock output locked to RCLK Interleaving PCM Bus Operation Per-channel loopback and idle code insertion 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola) Programmable output clocks for Fractional T1 ...
Description 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

File Size 1,015.62K  /  137 Page

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    HD74AC74

HITACHI[Hitachi Semiconductor]
Part No. HD74AC74
OCR Text ... been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to SD (Set) sets Q to High level Low ...
Description Dual D-Type Positive Edge-Triggered Flip-Flop

File Size 60.12K  /  10 Page

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    HD74CDCV857

HITACHI[Hitachi Semiconductor]
Part No. HD74CDCV857
OCR Text ...ce, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features * Supports 60 MHz to 200 MHz operation range * Distributes one differential clock inpu...
Description 2.5-V Phase-lock Loop Clock Driver

File Size 60.37K  /  15 Page

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    HDMP-1012 HDMP-1014

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1012 HDMP-1014
OCR Text ...ar Implementation On-chip Phase-locked Loops - Transmit Clock Generation - Receive Clock Extraction Description The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communicati...
Description 4Low Cost Gigabit Rate Transmit/Receive Chip Set

File Size 292.88K  /  42 Page

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    HDMP-1022 HDMP-1024

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1022 HDMP-1024
OCR Text ...ar Implementation On-Chip Phase-locked Loops - Transmit Clock Generation - Receive Clock Extraction data. Parallel data (a frame) loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can ...
Description Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

File Size 292.53K  /  40 Page

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    HDMP-1512 HDMP-1514

Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
Part No. HDMP-1512 HDMP-1514
OCR Text ...er Driver, and monolithic Phase locked loop clock generator. The actual operation of each function changes slightly, according to the desired configuration and option settings. Figures 18 and 19 show schematically how to terminate each pin ...
Description Fibre Channel Transmitter and Receiver Chipset

File Size 245.24K  /  26 Page

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