| OCR Text |
...s, data I/Os, chip enables (E1, e2, e3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power dow... |
| Description |
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 32 CACHE SRAM, 5.5 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 6 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 5.5 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 7.5 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 7 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 36 CACHE SRAM, 7 ns, PQFP100 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 32 CACHE SRAM, 7 ns, PQFP100
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