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Zarlink Semiconductor Inc.
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| Part No. |
MT9045
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| OCR Text |
...al reference selected reference dpll
mt9045 data sheet 2 zarlink semiconductor inc. description the mt9045 t1/e1/oc3 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization signals for mu... |
| Description |
T1/E1/OC3 System Synchronizer
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| File Size |
298.98K /
34 Page |
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Zarlink Semiconductor Inc.
Zarlink Semiconductor, Inc.
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| Part No. |
MT9043 MT9043AN48PINSSOP
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the mt9043 generates st-bus clock and framing signals that are phase locked to either a 19.4... |
| Description |
T1/E1 System Synchronizer T1/E1的系统同
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| File Size |
270.65K /
29 Page |
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Zarlink
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| Part No. |
MT9040
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| OCR Text |
...ns a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048... |
| Description |
T1/E1 Synchronizer
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| File Size |
373.11K /
28 Page |
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it Online |
Download Datasheet |
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Zarlink Semiconductor Inc.
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| Part No. |
MT9040
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for t1 and e1 primary rate transmission links. the mt9040 generates st-bus clock and framing signals that are phase locked to either a 19.44 mhz, 2.0... |
| Description |
T1/E1 Synchronizer
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| File Size |
244.63K /
27 Page |
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it Online |
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Fujitsu Limited
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| Part No. |
MB86H23
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| OCR Text |
... integrated s/p-dif interface, dpll, and internal audio dac?s. this helps to reduce product cost by eliminating the need for external components. the smartmpeg adds also dpll functionality, secam encoding, and two smart-card interface to... |
| Description |
MPEG-2 Decoder with Macrovision
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| File Size |
161.77K /
2 Page |
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Zarlink Semiconductor Inc.
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| Part No. |
MT9046 MT9046AN
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the device has reference switching and frequency holdover capabilities to help maintain conn... |
| Description |
T1/E1 System Synchronizer with Holdover
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| File Size |
307.19K /
34 Page |
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it Online |
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Zarlink
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| Part No. |
MT9042C
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| OCR Text |
...ns a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.04... |
| Description |
Multitrunk System Synchronizer
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| File Size |
533.79K /
28 Page |
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it Online |
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Zarlink
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| Part No. |
MT9046
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| OCR Text |
...ns a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain conne... |
| Description |
T1/E1 System Synchronizer with Holdover
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| File Size |
430.33K /
34 Page |
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it Online |
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IDT
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| Part No. |
IDT82V3002A
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| OCR Text |
...ns a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The IDT82V3002A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, ... |
| Description |
WAN PLL WITH DUAL REFERENCE INPUTS
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| File Size |
330.42K /
28 Page |
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it Online |
Download Datasheet |
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